In packaging a semiconductor device, the semiconductor device is usually mounted on a substrate high in heat conductivity, i.e., a heat sink to efficiently dissipate the heat emitted from the semiconductor device. Further by interposing a small heat sink, so called sub-mount, between the heat sink and the semiconductor device, the heat is further efficiently dissipated. Aluminum nitride (AlN) or others is used as such a heat sink high in heat conductivity.
If a heat sink having a semiconductor device chip mounted thereon is to be connected with the semiconductor device chip or a heat sink is to be connected with a cooling plate, they are connected together via a solder layer formed on one or each of both sides of the heat sink. In the interest of reducing its load on the environment it is proposed that the solder layer is formed of a lead (Pb) free solder e.g., Au—Sn, Ag—Sn, In—Sn or Zn—Sn solder.
In the case where an electrode layer made of gold (Au) is formed on the heat sink or the sub-mount substrate and is formed thereon with a solder layer of Pb free solder such as Au—Sn, Non-patent Reference 1 reports that gold of the electrode layer easily diffuses into the solder layer which itself is in non-equilibrium state and which will progress into equilibrium state if left at room temperature.
And, in the case where a solder layer of Au—Sn is formed on an electrode layer of Au as the uppermost layer, gold of the electrode layer diffuses into the solder layer, modifying the composition of the solder layer. Consequently, the composition proportion of gold in the solder layer is increased by gold diffusing into the Au—Sn solder layer, thereby raising the melting point of the solder layer itself. For this reason, the need has arisen to solder a semiconductor device at a temperature higher than the melting point determined by the composition of Au—Sn first formed. As a result, the temperature difference from the heat resistant temperature of a semiconductor device is reduced, giving rise to the problem of a defect in the semiconductor device.
To prevent interdiffusion between a solder layer and an electrode layer, it is known to provide an electrode structure that a solder barrier layer is formed between the solder and electrode layers.
FIG. 8 is a cross sectional view diagrammatically illustrating a structure of a sub-mount 50 having a conventional solder barrier layer. The conventional sub-mount 50 comprises a sub-mount substrate 51; an adherent layer 52 formed on an upper surface of the sub-mount substrate 51, namely on a surface of its side on which a semiconductor device is to be mounted; an electrode layer 53 formed on the adherent layer 52; a solder barrier layer 54 formed on the electrode layer 53; and a solder layer 55 formed on the solder barrier layer 54. The solder barrier layer 54 is composed of platinum (Pt) or palladium (Pd) to prevent gold of which the electrode layer 53 is composed from diffusing into the solder layer 55, thereby preventing the rise in melting point of the solder layer.
Patent Reference 1 discloses a technique in which a noble metal such as platinum or palladium as a solder barrier layer and a transition metal element such as titanium (Ti) as an adherent layer directly beneath the solder layer are deposited to raise the bonding strength of a sub-mount and a semiconductor device to be mounted thereon to 40 MPa or more.
Patent Reference 1: Japanese Patent No. JP 3509809 B
Non-patent Reference 1: S. Nakahara and three others “ROOM TEMPERATURE INTERDIFFUSION STUDIES OF Au/Sn THIN FILM COUPLES”, Thin Solid Films, Vol. 84, pp 185-196, 1981.